THETA — Foundry PADP
Region III field-computing experimental package: 7-tile G60 MODULE on active interposer, CV-primary readout, 25 GHz spacing, liquid-assist cooling, PACKAGE layer conventions (_ldrc03), post-trim mandatory beyond foundry CD spec.
Platform summary
7-tile G60 MODULE
Tiles: 7
4–6 W
Active interposer MODULE
Detection stack
CV-primary: 32 BHD + 256 SPAD (64× mux)
F-H01
F-H02Layer stack & materials
Shared L0–L11 platform across all eight PADPs — Si₃N₄ backbone, TFLN control, As₂S₃ LoCA BEOL (<210°C golden rule), optional AlGaAs MTP.
| Layer | Description |
|---|---|
| 7-tile G60 | Active interposer with routing + TEC + liquid channels |
| PACKAGE layer | LDRC03 conventions — multi-zone TEC hardware (D03) |
| BEOL | 24–40 LoCA + 20–32 AlGaAs MTP — nonlinear area exceeds linear |
StackDevice library
On-chip component inventory — status labels per R25 honesty audit.
| Device | Specification | Status |
|---|---|---|
| Active interposer | Routing + TEC + liquid assist — not passive Si | designed/target |
| CV readout | 32 BHD primary; 256 SPAD herald (64× mux) | designed/target |
| ChiL witnesses | 65k pairs → ~2k sampled witnesses + learned cal | designed/target |
| Squeezing | On-chip squeezing budget — OPC margin tightens | claim |
| Post-trim | CD beyond foundry spec — UV/thermal trim mandatory | to-be-tested |
Split-fab phases & assembly
Ligentec FEOL → QLT TFLN bond → arsenic-isolated As₂S₃ BEOL → hermetic package. Foundry never sees arsenic, LN donor recipes, or full OPC geometry.
LIGENTEC AN350
L0–L7 Si₃N₄ FEOL
QC: Gate 0 DRC/LVS/MRC pre-tapeout
→ Planarized wafer or diced dies
QLT bond bay
L8 TFLN ion-cut bond ≤500°C
QC: Gate 1B bond yield + adiabatic IL
→ 18+ EO sites bonded
QLT arsenic BEOL
L9 metal + L10 As₂S₃ <210°C
QC: Gate 2 OPC G≥+2 dB classical
→ Processed dies with LoCA fill
QLT assembly
Dice · fiber · SPAD · seal
QC: Gate 3 packaged acceptance
→ Hermetic module + test report
Active interposer assembly: 7 KGD-tested tiles → active interposer bond (routing + TEC + liquid channels) → MODULE-level pump distribution → CV calibration campaign. R28 package-layer memo defines ICD traceability.
AssemblyFoundry requirements & intake gates
What the foundry receives vs. what QLT retains. Partial GDS via encrypted transport.
| Item | Requirement / status |
|---|---|
| Posture | Roadmap appendix — experimental co-development |
| 300 mm fork | Held open from THETA for AIM-class interposer |
| PACKAGE ICD | STEP/DXF held — checklist-level only in Rev B2 |
| Gates | Active interposer bring-up before MODULE integration |
Campaign intake gates (all chips)
| Gate | Requirement | Status |
|---|---|---|
| Intake checklist | 00-FOUNDRY-INTAKE-CHECKLIST.md completed per chip/foundry | Open |
| NDA / PDK | DKLA executed; active rule deck downloaded and versioned | Open |
| Gate 0 | Partial-GDS export, DRC/LVS, Q-layer strip audit, SHA-256 hash | Open |
| Wafer probe / KGD | Per-die disposition traveler (mandatory NOVA+) | Open / N/A |
| Package ICD | Fiber, electrical, thermal, mechanical interfaces as drawings | Open |
| ATP / OQC | Acceptance matrix, soak, fiber pull, hermetic/leak tests | Open |
| Foundry acceptance | Module order, waiver list, COA format, quote in writing | Open |
Open items FQ-01–FQ-08 centralized in 00-FOUNDRY-INTAKE-CHECKLIST.md §9. PDK assumption freeze (AN350/AN800 layer integers, LoCA limits, CD/overlay) is a hard hold before GDS upload. Partial-GDS boundary must be DRC-debuggable without releasing withheld As₂S₃/TFLN/AlGaAs/control maps.
Five-volume structure
Full specs in Foundry Chip Docs/THETA/QLT-THETA-PADP-Vol-*
| Volume | Title | Research memos |
|---|---|---|
| Vol I | System Architecture | R01–R04 · blocks, encoding, I/O, power/thermal/package |
| Vol II | Physical Architecture | R05–R09 · layer stack, TFLN, LoCA, floorplan, thermal/electrical |
| Vol III | Device Library | R10–R16 · rings, AWG, mesh, couplers, modulators, OPC, detectors |
| Vol IV | Foundry Requirements | R17–R20 · Ligentec/AIM matrix, custom modules, DRC/IP |
| Vol V | Simulation & Tape-Out | R21–R25 · sim plans, GDS roadmap, honesty audit |
Tape-out readiness & honesty audit
H1 demux-256, H2 squeezing budget, H3 mux-holo-spot — schematic.
No fabricated simulation results are claimed in Vol V — all campaigns status=planned. No GDS beyond v0.1 heritage layouts. No foundry DRC signoff. Promotion path requires closing gates in THETA-PADP-ROLLUP.md.
F-H03
F-H04Cross-links
Foundry Chip Docs · Rev B2
On-disk package: Foundry Chip Docs/THETA/ · Bundle: _export/QLT-PADP-RevB2-2026-06-11.zip