Eight chips, one architecture
The QLT roadmap scales a single photonic processor design from d=2 dual-rail qubits (GEMINI) to d=512 rack-scale clusters (LOTUS) — progressing through the STAR-PHASER region into the full QUASAR framework. Each chip targets a specific Galois-field dimension, encoding strategy, and manufacturing readiness level.
Three chips lead, five follow
QLT's manufacturing strategy prioritizes the three chips closest to production: GEMINI (shipping today), GALAXY (design complete — QUASAR-transition prototype), and TETRIS (design complete — AWG scaling stress test). The remaining five — SOLAR, NOVA, SUPER, THETA, and LOTUS — advance through design and research stages in sequence, each inheriting validated fab processes from its predecessors.
STAR-PHASER → QUASAR ladder
Eight chips across four operating regions ● each card links to full specifications.
STAR-PHASER · Region I
4 Chips · d = 2–32GEMINI
→GF(2) dual-rail path qubit, 8-mode Clements mesh. The foundational chip — production-ready and shipping today. Validates the entire STAR-PHASER architecture at the simplest non-trivial dimension.
View full specificationsGALAXY
→GF(2⁴) frequency-bin encoding, 16-channel AWG demux. Design complete — the designated QUASAR-transition prototype. First chip to carry four qubits per photon in a frequency-bin basis.
View full specificationsTETRIS
→GF(2⁵) frequency-bin encoding, 32-channel AWG. Design complete — the AWG scaling stress test that proves dense channel packing before crossing into Region II territory.
View full specificationsSOLAR
→GF(11) 10-tooth frequency comb, decimal encoding pioneer. In development — explores prime-field arithmetic for applications where base-10 native computation eliminates conversion overhead.
View full specificationsQUASAR · Region II–IV
4 Chips · d = 64–512NOVA
→GF(2⁶) — the first Region II chip. In development — primary WS12 synthesis target. Crosses the threshold where OPC error correction becomes mandatory for meaningful gate fidelity.
View full specificationsSUPER
→GF(2⁷) dual C+L band operation. In development — OPC and squeezing both mandatory. The first chip requiring multi-band spectral management to fit all frequency channels.
View full specificationsTHETA
→GF(2⁸) 7-tile MODULE architecture. Research stage — field computing at Q≈1. First chip requiring multi-die assembly, pushing the QUASAR framework into modular territory.
View full specificationsLOTUS
→GF(2⁹) rack-scale cluster. Research horizon — tri-band soliton comb source spanning C+L+S bands. The ultimate expression of the QUASAR architecture at maximum photonic density.
View full specificationsSplit-fab, three-phase strategy
Every chip follows the same foundry model — Ligentec FEOL, QLT BEOL — scaled to match each chip's complexity tier.
Split-fab design
Ligentec handles front-end-of-line (FEOL) Si₃N₄ waveguide fabrication under encrypted GDS-II transfer. QLT performs all back-end-of-line (BEOL) integration — hybrid bonding, active alignment, and packaging — in-house, preserving full IP control.
Manufacturing travelers
Each chip has a dedicated manufacturing page detailing the complete fab process — from wafer preparation through final test. Process travelers, yield models, and equipment specifications are maintained per-chip.
Deep-dive into any chip or fab process
Each chip page contains complete optical parameters, gate architectures, encoding tables, and error budgets. Manufacturing pages detail every fab step from wafer to packaged die.