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Confidential · Foundry & Partner Access

SUPER PADP — foundry submission package

PADP Rev B2 foundry submission materials — layer stack, device library, split-fab assembly, and intake gates. Proposal-grade; not a mask order or GDS portal package. Enter the access password to continue.

Confidential · Foundry Chip Docs · PADP Rev B2

SUPER — Foundry PADP

C+L dual-band QUASAR at d=128: 4-tile layout, 35 GHz spacing, seam-lock subsystem, 5-zone TEC, KGD mandatory (FPY ~1–2% without). Roadmap appendix — risk framing, not immediate MPW ask.

d=128 GF(2⁷) prime-degree QUASAR Region II high-risk (~0.50) Challenging

Foundry posture: Roadmap appendix. Source corpus: Foundry Chip Docs/SUPER/ — five PADP volumes + R01–R25 research memos + SUPER-PADP-ROLLUP.md. Cross-chip context: 00-CROSS-CHIP-ROLLUP.md.

Chip identity

Platform summary

Die / reticle

4-tile G46 scaled

Tiles: 4

Power · package

2.5–4 W

Scaled 2.5D interposer

Readout

Detection stack

128 SPAD (32× mux) + 16 BHD

F-U01F-U01
F-U01. 4-tile C+L dual-band floorplan placeholder · Rev B2
F-U02F-U02
F-U02. Seam-lock optical junction cross-section placeholder · Rev B2
Parts · Vol II

Layer stack & materials

Shared L0–L11 platform across all eight PADPs — Si₃N₄ backbone, TFLN control, As₂S₃ LoCA BEOL (<210°C golden rule), optional AlGaAs MTP.

LayerDescription
4-tile FEOLC-band + L-band dual-source tiles
InterposerScaled 2.5D — seam-lock optical + thermal
BEOL16–24 LoCA + 14–22 AlGaAs MTP
StackStack
Layer stack cross-section. L0–L11 material stack for SUPER. placeholder
Parts · Vol III

Device library

On-chip component inventory — status labels per R25 honesty audit.

DeviceSpecificationStatus
Dual combC+L dual-band source; B_comb ≈ 4.45 THzdesigned/target
Seam lockPhase-coherent stitch across 4 tilesdesigned/target
5-zone TECIndependent thermal zonesdesigned/target
Demux 128128-bin readout pathdesigned/target
Holographic readoutPartial holographic mux optionroadmap
Assembly · R19

Split-fab phases & assembly

Ligentec FEOL → QLT TFLN bond → arsenic-isolated As₂S₃ BEOL → hermetic package. Foundry never sees arsenic, LN donor recipes, or full OPC geometry.

Phase A

LIGENTEC AN350

L0–L7 Si₃N₄ FEOL

QC: Gate 0 DRC/LVS/MRC pre-tapeout

→ Planarized wafer or diced dies

Phase B

QLT bond bay

L8 TFLN ion-cut bond ≤500°C

QC: Gate 1B bond yield + adiabatic IL

→ 18+ EO sites bonded

Phase C

QLT arsenic BEOL

L9 metal + L10 As₂S₃ <210°C

QC: Gate 2 OPC G≥+2 dB classical

→ Processed dies with LoCA fill

Phase D

QLT assembly

Dice · fiber · SPAD · seal

QC: Gate 3 packaged acceptance

→ Hermetic module + test report

SUPER-specific assembly notes

KGD mandatory — do not assemble untested dies. Seam-lock calibration is critical path. 5-zone TEC co-control firmware on FPGA.

AssemblyAssembly
Assembly flow. Split-fab cut line and package integration for SUPER. placeholder
Foundry instructions · Vol IV

Foundry requirements & intake gates

What the foundry receives vs. what QLT retains. Partial GDS via encrypted transport.

ItemRequirement / status
PostureRoadmap appendix — co-development orientation only
KGDMandatory — FPY economics require per-die disposition
RiskRegion II high-risk Q ~0.50 — OPC/squeezing co-equal with linear mesh
GatesSeam-lock witness structures on each tile

Campaign intake gates (all chips)

GateRequirementStatus
Intake checklist00-FOUNDRY-INTAKE-CHECKLIST.md completed per chip/foundryOpen
NDA / PDKDKLA executed; active rule deck downloaded and versionedOpen
Gate 0Partial-GDS export, DRC/LVS, Q-layer strip audit, SHA-256 hashOpen
Wafer probe / KGDPer-die disposition traveler (mandatory NOVA+)Open / N/A
Package ICDFiber, electrical, thermal, mechanical interfaces as drawingsOpen
ATP / OQCAcceptance matrix, soak, fiber pull, hermetic/leak testsOpen
Foundry acceptanceModule order, waiver list, COA format, quote in writingOpen
Foundry question register

Open items FQ-01–FQ-08 centralized in 00-FOUNDRY-INTAKE-CHECKLIST.md §9. PDK assumption freeze (AN350/AN800 layer integers, LoCA limits, CD/overlay) is a hard hold before GDS upload. Partial-GDS boundary must be DRC-debuggable without releasing withheld As₂S₃/TFLN/AlGaAs/control maps.

PADP package index

Five-volume structure

Full specs in Foundry Chip Docs/SUPER/QLT-SUPER-PADP-Vol-*

VolumeTitleResearch memos
Vol ISystem ArchitectureR01–R04 · blocks, encoding, I/O, power/thermal/package
Vol IIPhysical ArchitectureR05–R09 · layer stack, TFLN, LoCA, floorplan, thermal/electrical
Vol IIIDevice LibraryR10–R16 · rings, AWG, mesh, couplers, modulators, OPC, detectors
Vol IVFoundry RequirementsR17–R20 · Ligentec/AIM matrix, custom modules, DRC/IP
Vol VSimulation & Tape-OutR21–R25 · sim plans, GDS roadmap, honesty audit
Simulation · Vol V

Tape-out readiness & honesty audit

Rev B2 status — proposal-grade

U1 demux-128, U2 L-band dual-comb, U3 readout holo — schematic.

No fabricated simulation results are claimed in Vol V — all campaigns status=planned. No GDS beyond v0.1 heritage layouts. No foundry DRC signoff. Promotion path requires closing gates in SUPER-PADP-ROLLUP.md.

F-U03F-U03
F-U03. C+L dual soliton comb architecture placeholder · Rev B2
F-U04F-U04
F-U04. 5-zone TEC thermal control map placeholder · Rev B2
Related pages

Cross-links

Product

SUPER product ref

Customer-facing architecture and competitive positioning.

Manufacturing

SUPER fab path

Equipment, process traveler, and in-house BEOL steps.

Campaign

Chip lineup

8-chip dimension ladder and QUASAR framework context.

Source corpus

Foundry Chip Docs · Rev B2

On-disk package: Foundry Chip Docs/SUPER/ · Bundle: _export/QLT-PADP-RevB2-2026-06-11.zip

Manufacturing overviewNext PADP →