TETRIS — Foundry PADP
Terminal pure STAR-PHASER reticle: d=32 fills one 5×10 mm reticle (~44–52 mm²). 6–12 LoCA OPC sites, passive-cooling limit demonstrated in thermal sims. Last chip before mandatory multi-tile QUASAR transition at NOVA.
Platform summary
5 × 10 mm reticle fill (~90–98%)
Tiles: 1
< 1.4 W
CQFP / LTCC + lid
Detection stack
32-ch SPAD (8× mux)
F-T01
F-T02Layer stack & materials
Shared L0–L11 platform across all eight PADPs — Si₃N₄ backbone, TFLN control, As₂S₃ LoCA BEOL (<210°C golden rule), optional AlGaAs MTP.
| Layer | Description |
|---|---|
| L0–L7 | Maximum-density SiN routing — reticle fill optimization |
| L8–L10 | TFLN + 6–12 LoCA windows (no AlGaAs on v1) |
StackDevice library
On-chip component inventory — status labels per R25 honesty audit.
| Device | Specification | Status |
|---|---|---|
| Demux | 32-bin cascaded microring or AWG hybrid | designed/target |
| LoCA OPC | 6–12 nonlinear sites; no AlGaAs v1 | designed/target |
| Thermal | Passive + lid — reticle hotspot management | designed/target |
| ChiL pairs | 992 directed calibration pairs | designed/target |
| Mux model | 32→1 readout tree with 8× SPAD mux | designed/target |
Split-fab phases & assembly
Ligentec FEOL → QLT TFLN bond → arsenic-isolated As₂S₃ BEOL → hermetic package. Foundry never sees arsenic, LN donor recipes, or full OPC geometry.
LIGENTEC AN350
L0–L7 Si₃N₄ FEOL
QC: Gate 0 DRC/LVS/MRC pre-tapeout
→ Planarized wafer or diced dies
QLT bond bay
L8 TFLN ion-cut bond ≤500°C
QC: Gate 1B bond yield + adiabatic IL
→ 18+ EO sites bonded
QLT arsenic BEOL
L9 metal + L10 As₂S₃ <210°C
QC: Gate 2 OPC G≥+2 dB classical
→ Processed dies with LoCA fill
QLT assembly
Dice · fiber · SPAD · seal
QC: Gate 3 packaged acceptance
→ Hermetic module + test report
Reticle-terminal layout — no tile stitch. Thermal lid optional for hotspot flattening. Demonstrates passive-cooling ceiling for STAR-PHASER ladder.
AssemblyFoundry requirements & intake gates
What the foundry receives vs. what QLT retains. Partial GDS via encrypted transport.
| Item | Requirement / status |
|---|---|
| Primary | LIGENTEC AN350 — reticle MRC critical |
| Transition note | Last single-die STAR-PHASER; NOVA requires 3-tile G46 |
| DRC | Density/fill at reticle limit — waiver register may apply |
| Gates | Thermal reticle sim gate before tape-out |
Campaign intake gates (all chips)
| Gate | Requirement | Status |
|---|---|---|
| Intake checklist | 00-FOUNDRY-INTAKE-CHECKLIST.md completed per chip/foundry | Open |
| NDA / PDK | DKLA executed; active rule deck downloaded and versioned | Open |
| Gate 0 | Partial-GDS export, DRC/LVS, Q-layer strip audit, SHA-256 hash | Open |
| Wafer probe / KGD | Per-die disposition traveler (mandatory NOVA+) | Open / N/A |
| Package ICD | Fiber, electrical, thermal, mechanical interfaces as drawings | Open |
| ATP / OQC | Acceptance matrix, soak, fiber pull, hermetic/leak tests | Open |
| Foundry acceptance | Module order, waiver list, COA format, quote in writing | Open |
Open items FQ-01–FQ-08 centralized in 00-FOUNDRY-INTAKE-CHECKLIST.md §9. PDK assumption freeze (AN350/AN800 layer integers, LoCA limits, CD/overlay) is a hard hold before GDS upload. Partial-GDS boundary must be DRC-debuggable without releasing withheld As₂S₃/TFLN/AlGaAs/control maps.
Five-volume structure
Full specs in Foundry Chip Docs/TETRIS/QLT-TETRIS-PADP-Vol-*
| Volume | Title | Research memos |
|---|---|---|
| Vol I | System Architecture | R01–R04 · blocks, encoding, I/O, power/thermal/package |
| Vol II | Physical Architecture | R05–R09 · layer stack, TFLN, LoCA, floorplan, thermal/electrical |
| Vol III | Device Library | R10–R16 · rings, AWG, mesh, couplers, modulators, OPC, detectors |
| Vol IV | Foundry Requirements | R17–R20 · Ligentec/AIM matrix, custom modules, DRC/IP |
| Vol V | Simulation & Tape-Out | R21–R25 · sim plans, GDS roadmap, honesty audit |
Tape-out readiness & honesty audit
T1 demux trade, T2 thermal reticle, T3 mux model — schematic tier.
No fabricated simulation results are claimed in Vol V — all campaigns status=planned. No GDS beyond v0.1 heritage layouts. No foundry DRC signoff. Promotion path requires closing gates in TETRIS-PADP-ROLLUP.md.
F-T03
F-T04Cross-links
Foundry Chip Docs · Rev B2
On-disk package: Foundry Chip Docs/TETRIS/ · Bundle: _export/QLT-PADP-RevB2-2026-06-11.zip