NOVA — Foundry PADP
First QUASAR chip and first mandatory multi-tile assembly: 3-tile G46 (SOURCE / QFP / READOUT) on a 2.5D interposer. Soliton comb Route B primary, μTEC zoning, dual readout (SPAD + balanced homodyne), KGD policy begins.
Platform summary
3-tile G46 on 2.5D interposer
Tiles: 3
1.5–2.5 W
2.5D Si interposer
Detection stack
64 SPAD + 8 BHD
F-N01
F-N02Layer stack & materials
Shared L0–L11 platform across all eight PADPs — Si₃N₄ backbone, TFLN control, As₂S₃ LoCA BEOL (<210°C golden rule), optional AlGaAs MTP.
| Layer | Description |
|---|---|
| Per-tile FEOL | 3× AN350 dies — phase-coherent stitch junctions |
| Interposer | 2.5D Si — optical + electrical routing between tiles |
| BEOL | 10–14 LoCA + 8–14 AlGaAs MTP sites across tiles |
| Package | μTEC zones; fiber fan-out; BHD LO tap from pump |
StackDevice library
On-chip component inventory — status labels per R25 honesty audit.
| Device | Specification | Status |
|---|---|---|
| 3-tile stitch | G46 SOURCE + QFP + READOUT; seam-lock subsystem | designed/target |
| Soliton comb | Route B LLE — primary source architecture | designed/target |
| LoCA + MTP | 10–14 LoCA; 8–14 AlGaAs production return | designed/target |
| μTEC | Zoned thermoelectric cooling — Region II entry | designed/target |
| Dual readout | 64 SPAD + 8 BHD channels | designed/target |
| KGD | Known-good-die test mandatory before assembly | to-be-tested |
Split-fab phases & assembly
Ligentec FEOL → QLT TFLN bond → arsenic-isolated As₂S₃ BEOL → hermetic package. Foundry never sees arsenic, LN donor recipes, or full OPC geometry.
LIGENTEC AN350
L0–L7 Si₃N₄ FEOL
QC: Gate 0 DRC/LVS/MRC pre-tapeout
→ Planarized wafer or diced dies
QLT bond bay
L8 TFLN ion-cut bond ≤500°C
QC: Gate 1B bond yield + adiabatic IL
→ 18+ EO sites bonded
QLT arsenic BEOL
L9 metal + L10 As₂S₃ <210°C
QC: Gate 2 OPC G≥+2 dB classical
→ Processed dies with LoCA fill
QLT assembly
Dice · fiber · SPAD · seal
QC: Gate 3 packaged acceptance
→ Hermetic module + test report
Multi-tile assembly flow: fabricate 3 dies → wafer probe / KGD disposition → interposer bond → optical seam alignment → package with μTEC → dual readout calibration. First chip where MPW economics break — dedicated lot recommended.
AssemblyFoundry requirements & intake gates
What the foundry receives vs. what QLT retains. Partial GDS via encrypted transport.
| Item | Requirement / status |
|---|---|
| Primary | LIGENTEC 3-die + AIM interposer/TAP backup |
| KGD traveler | Hard gate before multi-tile assembly (intake checklist §6) |
| Stitch | Phase-coherent tile junction — first-class platform technology |
| AIM role | Interposer grows monotonically from NOVA onward |
| Gates | Per-tile DRC + interposer ICD + KGD probe spec |
Campaign intake gates (all chips)
| Gate | Requirement | Status |
|---|---|---|
| Intake checklist | 00-FOUNDRY-INTAKE-CHECKLIST.md completed per chip/foundry | Open |
| NDA / PDK | DKLA executed; active rule deck downloaded and versioned | Open |
| Gate 0 | Partial-GDS export, DRC/LVS, Q-layer strip audit, SHA-256 hash | Open |
| Wafer probe / KGD | Per-die disposition traveler (mandatory NOVA+) | Open / N/A |
| Package ICD | Fiber, electrical, thermal, mechanical interfaces as drawings | Open |
| ATP / OQC | Acceptance matrix, soak, fiber pull, hermetic/leak tests | Open |
| Foundry acceptance | Module order, waiver list, COA format, quote in writing | Open |
Open items FQ-01–FQ-08 centralized in 00-FOUNDRY-INTAKE-CHECKLIST.md §9. PDK assumption freeze (AN350/AN800 layer integers, LoCA limits, CD/overlay) is a hard hold before GDS upload. Partial-GDS boundary must be DRC-debuggable without releasing withheld As₂S₃/TFLN/AlGaAs/control maps.
Five-volume structure
Full specs in Foundry Chip Docs/NOVA/QLT-NOVA-PADP-Vol-*
| Volume | Title | Research memos |
|---|---|---|
| Vol I | System Architecture | R01–R04 · blocks, encoding, I/O, power/thermal/package |
| Vol II | Physical Architecture | R05–R09 · layer stack, TFLN, LoCA, floorplan, thermal/electrical |
| Vol III | Device Library | R10–R16 · rings, AWG, mesh, couplers, modulators, OPC, detectors |
| Vol IV | Foundry Requirements | R17–R20 · Ligentec/AIM matrix, custom modules, DRC/IP |
| Vol V | Simulation & Tape-Out | R21–R25 · sim plans, GDS roadmap, honesty audit |
Tape-out readiness & honesty audit
N1 demux scaling, N2 μTEC zoning, N3 dual-readout — schematic.
No fabricated simulation results are claimed in Vol V — all campaigns status=planned. No GDS beyond v0.1 heritage layouts. No foundry DRC signoff. Promotion path requires closing gates in NOVA-PADP-ROLLUP.md.
F-N03
F-N04Cross-links
Foundry Chip Docs · Rev B2
On-disk package: Foundry Chip Docs/NOVA/ · Bundle: _export/QLT-PADP-RevB2-2026-06-11.zip