LOTUS — Foundry PADP
Research Definition Package — not an engineering tape-out ask. d=512 S+C+L tri-band cluster, replaceable NL cartridges, liquid cooling baseline, S-band 1490 nm pump plan (R27), lab instrumentation BOMs (F03/F09), availability economics replace FPY.
Platform summary
10–14 tiles / 2–4 module cluster
Tiles: 10–14
8–12 W
CLUSTER + backplane
Detection stack
64 BHD + 512 SPAD herald (128× mux)
F-L01
F-L02Layer stack & materials
Shared L0–L11 platform across all eight PADPs — Si₃N₄ backbone, TFLN control, As₂S₃ LoCA BEOL (<210°C golden rule), optional AlGaAs MTP.
| Layer | Description |
|---|---|
| Cluster | 2–4 MODULE units on active interposer backplane |
| NL cartridges | Replaceable As₂S₃/AlGaAs tiles — photodarkening lifetime 25–120 h |
| S-band pump | 1490 nm DFB pump plant — R27 pump plan + P01–P25 memos |
| Tri-band | S+C+L; B_comb ≈ 10.2 THz; 20 GHz spacing |
StackDevice library
On-chip component inventory — status labels per R25 honesty audit.
| Device | Specification | Status |
|---|---|---|
| 512-bin demux | L1 demux scaling — crosstalk critical path | designed/target |
| Tri-comb | S+C+L soliton combs; edge coupler S-band (P4S) | designed/target |
| NL cartridges | 40–64 LoCA + 32–52 MTP — field-replaceable | roadmap |
| Pump integration | T0–T3 ladder (P19); vendor matrix (P22) | designed/target |
| Lab BOM | F03 instrumentation ~$4–9k; F09 SIL bench optics | designed/target |
| Readout | CV-only-witness: 64 BHD + 512 herald SPAD | designed/target |
Split-fab phases & assembly
Ligentec FEOL → QLT TFLN bond → arsenic-isolated As₂S₃ BEOL → hermetic package. Foundry never sees arsenic, LN donor recipes, or full OPC geometry.
LIGENTEC AN350
L0–L7 Si₃N₄ FEOL
QC: Gate 0 DRC/LVS/MRC pre-tapeout
→ Planarized wafer or diced dies
QLT bond bay
L8 TFLN ion-cut bond ≤500°C
QC: Gate 1B bond yield + adiabatic IL
→ 18+ EO sites bonded
QLT arsenic BEOL
L9 metal + L10 As₂S₃ <210°C
QC: Gate 2 OPC G≥+2 dB classical
→ Processed dies with LoCA fill
QLT assembly
Dice · fiber · SPAD · seal
QC: Gate 3 packaged acceptance
→ Hermetic module + test report
Pump integration ladder T0 (bench) → T3 (cluster). Replaceable NL cartridge swap procedure. S-band DFB procurement gate (F08). Budget rollup F12. Liquid cooling baseline — no passive option.
AssemblyFoundry requirements & intake gates
What the foundry receives vs. what QLT retains. Partial GDS via encrypted transport.
| Item | Requirement / status |
|---|---|
| Posture | Research definition — not fabrication PO |
| Availability | Availability % replaces FPY as success metric |
| EDA | Commercial EDA coverage <25% — QLT internal field solver primary |
| Gates | G01–G10 pump-plan gates; F01–F12 lab-gate memos |
Campaign intake gates (all chips)
| Gate | Requirement | Status |
|---|---|---|
| Intake checklist | 00-FOUNDRY-INTAKE-CHECKLIST.md completed per chip/foundry | Open |
| NDA / PDK | DKLA executed; active rule deck downloaded and versioned | Open |
| Gate 0 | Partial-GDS export, DRC/LVS, Q-layer strip audit, SHA-256 hash | Open |
| Wafer probe / KGD | Per-die disposition traveler (mandatory NOVA+) | Open / N/A |
| Package ICD | Fiber, electrical, thermal, mechanical interfaces as drawings | Open |
| ATP / OQC | Acceptance matrix, soak, fiber pull, hermetic/leak tests | Open |
| Foundry acceptance | Module order, waiver list, COA format, quote in writing | Open |
Open items FQ-01–FQ-08 centralized in 00-FOUNDRY-INTAKE-CHECKLIST.md §9. PDK assumption freeze (AN350/AN800 layer integers, LoCA limits, CD/overlay) is a hard hold before GDS upload. Partial-GDS boundary must be DRC-debuggable without releasing withheld As₂S₃/TFLN/AlGaAs/control maps.
Five-volume structure
Full specs in Foundry Chip Docs/LOTUS/QLT-LOTUS-PADP-Vol-*
| Volume | Title | Research memos |
|---|---|---|
| Vol I | System Architecture | R01–R04 · blocks, encoding, I/O, power/thermal/package |
| Vol II | Physical Architecture | R05–R09 · layer stack, TFLN, LoCA, floorplan, thermal/electrical |
| Vol III | Device Library | R10–R16 · rings, AWG, mesh, couplers, modulators, OPC, detectors |
| Vol IV | Foundry Requirements | R17–R20 · Ligentec/AIM matrix, custom modules, DRC/IP |
| Vol V | Simulation & Tape-Out | R21–R25 · sim plans, GDS roadmap, honesty audit |
Tape-out readiness & honesty audit
L1 demux-512, L2 S-band tri-comb, L3 mux power, C4 LLE comb — schematic.
No fabricated simulation results are claimed in Vol V — all campaigns status=planned. No GDS beyond v0.1 heritage layouts. No foundry DRC signoff. Promotion path requires closing gates in LOTUS-PADP-ROLLUP.md.
F-L03
F-L04Cross-links
Foundry Chip Docs · Rev B2
On-disk package: Foundry Chip Docs/LOTUS/ · Bundle: _export/QLT-PADP-RevB2-2026-06-11.zip