LUV Language | Field-Theoretic Array Language for Photonic Processors ● Quantum Light Technology

What is LUV?

Galois fields over arrays of optical modes

Programmable photonic processors are controlled by analog quantities — heater phases on Mach–Zehnder meshes, spectral masks across frequency combs, heralded single-photon detection. Today these are hand-built in NumPy scripts with no semantic layer, no portability across chips, and no honesty about what is simulated versus designed.

LUV closes that gap. Its central claim: the correct abstraction is finite-field arithmetic acting on an array of optical modes. Every chip in the QLT ladder natively realizes GF(2^k) (or GF(11) on SOLAR), and every physical control primitive — MZI phase, comb-bin permutation, spectral hologram — is the image of an algebraic verb under a fixed lowering map.

Thin skin over QIL

No second semantics

Anything LUV expresses must lower to QIL IR 0.1.0. The IR — not the surface syntax — is the contract with the execution layer. galois/JAX remain the simulation engine; LUV is the programmer-facing skin.

Honesty discipline

Machine-readable provenance

Every compiled artifact carries [simulated], [model], or [designed/target] labels as JSON fields — not comments — so downstream tooling can refuse to mix grades.

Language

APL-flavored verbs for photonic hardware

UTF-8 text, one statement per line, # comments. Unicode glyphs and ASCII digraphs are interchangeable — luvc fmt canonicalizes to glyphs.

Glyph	ASCII	Meaning
←	<-	binding
⊕	(+)	GF add (XOR in char-2) — elementwise on arrays
⊗	(*)	GF multiply — elementwise on arrays
⌽	(<<)	cyclic rotate (dyadic: `k ⌽ v`)
⍉	(T)	matrix transpose (monadic)

Setup

target · field

target GEMINI sim selects chip and backend (sim or qpu). field 8 declares GF(2⁸) — fixing arithmetic, RS codes, qudit dimension, and legal chip targets in one line.

Hardware verbs

mesh · gate · hologram

mesh dft 8 → Clements synthesis. gate F_d 10 → QFP unitary. hologram e8 17 → E8 root phase mask. shift 3 → bin-grid permute.

Execution

shot · measure · when

shot seed 7 requests a heralded sample [simulated]. measure m0 destructures into a GF symbol. v0.3 when adds post-measure feedforward at the ~11.2 ns herald tier.

v0.3 additions

TDM holograms and feedforward

hologram time [r0 ; r1 ...] lowers to a TDMSequence — one phase-mask step per time slot for rank-2 freq×time programs. when m0 = K shift 1 lowers to a Feedforward IR op kept out of the pre-shot schedule; the runtime fires matching conditions against decoded measures and logs the [model] 11.2 ns budget.

Also: rs_encode / rs_decode, iota, emit, hologram amp [...] phase [...] for post-selected complex masks.

Compile pipeline

From `.luv` to hardware artifacts

luvc build emits one .qil.json bundle. Three hardware-facing artifacts are produced simultaneously.

1

`.luv` source

Line-oriented program with field, mesh/gate/hologram, shot.

2

`luvc` compile

Parse + constant fold GF expressions. Lower to QIL IR 0.1.0. Decompose into Clements phases, QFP schedule, DAC vector.

3

Three artifacts

dac.voltages[32]

28 Clements phases → crosstalk-corrected 0–5 V words for AD5372 [model]

qfp_schedule[]

Ordered unitary / phase_mask / amp_phase_mask / permute steps [simulated]

shot contract

SPAD pattern + comb_lock gate + post-selection probability [simulated]

4

`luvc run`

Digital twin execution: run_gemini_shot (mesh path) or run_freqbin_shot (gate-only path). Acceptance test for future FPGA firmware = agreement with luvc run.

LUV compiler pipeline: .luv source → luvc → QIL IR → DAC voltages, QFP schedule, shot contract — **Compile pipeline.** From `.luv` source through `luvc` to three hardware-facing artifacts.

luvc check luvc build luvc run luvc fmt

Examples

Programs that run today [simulated]

Runnable examples in _qil/luv/examples/. Build with luvc build, execute with luvc run.

gemini_shot.luv — hello photonics

8-mode DFT mesh + heralded shot on GEMINI

luv 0.1
target GEMINI sim
field 1                  # GF(2) — GEMINI baseline

mesh dft 8               # 8-mode DFT -> 28 Clements phases -> 32-ch DAC
shot seed 7              # torontonian SPAD sample [simulated]

The minimal LUV program: declare GF(2), synthesize an 8-mode discrete Fourier transform through the Clements mesh, and request one heralded single-photon detection event.

solar_rs.luv — error-corrected loop

RS(10,8) encode → gate → shot → measure → decode

luv 0.2
target SOLAR sim
field prime 11

let msg ← [3 1 4 1 5 9 2 6]
let cw  ← rs_encode msg
let back ← rs_decode cw          # syndrome check lands in rs_ok["back"]

gate F_d 10
shot seed 3
measure m0

The first fully error-corrected program loop: Reed–Solomon encode a message over GF(11), apply a photonic F_d gate on SOLAR's 10-bin comb, herald a shot, destructure the click into a GF symbol, and decode.

solar_feedforward.luv — v0.3 real-time control

TDM hologram + post-measure feedforward

when m0 = 0 shift 1      # if the click landed in bin 0, advance the grid
when m0 = 5 gate Z_d 10  # if it landed in bin 5, apply a Z_d frame

v0.3 conditionals land in the ~11.2 ns feedforward tier — one FPGA BRAM LUT row per when line. The simulator's stall semantics and post-selection bookkeeping are the behavioral spec for future firmware.

Chip ladder

One language, eight chips

A single field declaration fixes arithmetic, Reed–Solomon codes, qudit dimension, and legal targets. The field ladder is the type ladder.

Chip	Encoding	d	Field	LUV declaration
GEMINI	8-mode Clements mesh	2	GF(2)	`field 1`
SOLAR	10-tooth frequency comb	10	GF(11)	`field prime 11`
GALAXY	frequency-bin	16	GF(2⁴)	`field 4`
TETRIS	frequency-bin	32	GF(2⁵)	`field 5`
NOVA	frequency-bin	64	GF(2⁶)	`field 6`
SUPER	dual C+L band	128	GF(2⁷)	`field 7`
THETA	frequency-bin	256	GF(2⁸)	`field 8`
LOTUS	freq × time, rack-scale	512	GF(2⁹)	`field 9`

LUV chip field ladder: GEMINI GF(2) through LOTUS GF(2^9), STAR-PHASER to QUASAR — **One language, eight chips.** A single `field` declaration fixes arithmetic, RS codes, qudit dimension, and legal targets across the entire chip ladder.

Spatial path

GEMINI — Clements mesh

mesh dft N synthesizes exact unitaries via Clements 2016 decomposition. 28 active phases project to a 32-channel AD5372 DAC vector with crosstalk correction [model].

Frequency-bin path

SOLAR → LOTUS — QFP gates

gate X_d/Z_d/F_d D composes into a QFP schedule. Holograms lower to phase masks; v0.3 hologram time expands to slot-tagged TDM steps for rank-2 programs on LOTUS.

Runtime

Three timing tiers the language already encodes

LUV targets the artifact contract; the FPGA (or ASIC scheduler) consumes it. The simulator's stall semantics are the behavioral spec for future firmware.

Tier	Latency	LUV surface	Hardware path
Feedforward	~11.2 ns	`when` after `measure`	SPAD → 64 ps TDC → FPGA BRAM lookup → TFLN EO switch. Photon held in 3.5 ns delay spiral.
Reconfiguration	~54 µs	`mesh`, `phases`, DAC vector	FPGA → SPI → AD5372 → 32 heaters. Heater τ_rise ≈ 1 ms dominates settling.
Environment	<30 s → ~16 min	`comb_lock.grid_valid`	L0 TEC → L1 band heaters → L2 per-tooth servo. `grid_valid` is the hardware interlock — sequencer refuses opcodes when comb is not locked.

Three-tier FPGA timing architecture: feedforward 11.2ns, reconfiguration 54µs, environment 30s-16min — **Three timing tiers.** Feedforward (~11.2 ns), reconfiguration (~54 µs), and environment (<30 s – ~16 min) — all encoded in LUV keywords.

Control-plane ladder

FPGA means different things at each rung

On GEMINI–TETRIS, the Artix-7 FPGA is the control brain (32–112 DAC channels, SPAD readout). From NOVA upward, a companion ASIC owns the DAC bank while the FPGA schedules ChiL/RF. At THETA/LOTUS, a Versal-class scheduler orchestrates a multi-die ASIC set. LUV is insulated from this escalation — the artifact contract is identical at every rung.

Simulator = spec

Acceptance test = `luvc run`

When FPGA firmware exists, its acceptance test is byte-level agreement with the digital twin. Post-selection bookkeeping, measure-destructuring rules, and grid_valid stall semantics are already encoded in the simulation layer [simulated].

GEMINI: Artix-7 + 2× AD5372 · 24 SPAD → 64 ps TDC

Control-plane escalation: Artix-7 FPGA on GEMINI-TETRIS, FPGA+ASIC on NOVA-SUPER, Versal scheduler on THETA-LOTUS — **Control-plane escalation.** Hardware complexity grows from Artix-7 to Versal-class — but the LUV artifact contract stays identical at every rung.

Status & honesty

What exists today

No FPGA firmware is shipped. All execution results are digital-twin output until hardware bring-up.

[simulated]

Digital twin

Numbers produced by galois/JAX simulation: heralded shots, torontonian detection, exact Clements synthesis, freq-bin gate composition.

[model]

Engineering approximation

Hardware-subset 28-phase projection, thermal crosstalk matrices, AD5372 voltage encoding, feedforward latency budget.

[designed/target]

Design intent

Chip specifications, DAC channel counts, timing budgets, and control-plane architecture — unverified against silicon.

Version	Highlights	Status
v0.1	`mesh`, `shot`, GEMINI path	Shipped
v0.2	Array verbs (`⌽`, `⍉`, `iota`), RS codec, freq-bin gates, `measure`	Shipped
v0.3	`hologram time` (TDM), `when` feedforward, QFP→heater DAC lowering, AD5372 SPI frames	Current — 121-test suite green

[roadmap] homodyne measure variant [roadmap] qpu backend (silicon) [roadmap] nested conditionals

Partner inquiry

Explore the LUV toolchain

LUV is released for internal and partner circulation. The compiler, 121-test suite, VS Code syntax extension, and seven example programs are available in the QIL stack.

Contact QLT Platform Technology QUASAR Framework

Written in LUV, runs on light