GALAXY — Foundry PADP
First full-reticle STAR-PHASER chip at d=16: 50 GHz comb, 16-bin AWG network, first AlGaAs MTP rehearsal cells, and QUASAR-transition prototype features on a single 5×10 mm die.
Platform summary
5 × 10 mm full reticle
Tiles: 1
~1 W
CQFP / LTCC
Detection stack
16-ch SPAD
F-X01
F-X02Layer stack & materials
Shared L0–L11 platform across all eight PADPs — Si₃N₄ backbone, TFLN control, As₂S₃ LoCA BEOL (<210°C golden rule), optional AlGaAs MTP.
| Layer | Description |
|---|---|
| L0–L7 | AN350 damascene SiN on 5×10 mm reticle |
| L8 | TFLN control plane — scaled RF bus (8-tone harmonic) |
| L10 | Sparse As₂S₃ LoCA + 2–3 AlGaAs MTP rehearsal sites |
StackDevice library
On-chip component inventory — status labels per R25 honesty audit.
| Device | Specification | Status |
|---|---|---|
| AWG network | 16-ch demux/mux; AIM AWGR-class footprint | designed/target |
| AlGaAs MTP | 2–3 rehearsal nonlinear cells via micro-transfer print | to-be-tested |
| Comb / encoder | 50 GHz grid; B_comb ≈ 750 GHz | designed/target |
| OPC cells | Sparse LoCA — 2–3 sites | claim |
| ChiL calibration | ~240 directed phase pairs | designed/target |
| Detectors | 16-ch warm SPAD array | designed/target |
Split-fab phases & assembly
Ligentec FEOL → QLT TFLN bond → arsenic-isolated As₂S₃ BEOL → hermetic package. Foundry never sees arsenic, LN donor recipes, or full OPC geometry.
LIGENTEC AN350
L0–L7 Si₃N₄ FEOL
QC: Gate 0 DRC/LVS/MRC pre-tapeout
→ Planarized wafer or diced dies
QLT bond bay
L8 TFLN ion-cut bond ≤500°C
QC: Gate 1B bond yield + adiabatic IL
→ 18+ EO sites bonded
QLT arsenic BEOL
L9 metal + L10 As₂S₃ <210°C
QC: Gate 2 OPC G≥+2 dB classical
→ Processed dies with LoCA fill
QLT assembly
Dice · fiber · SPAD · seal
QC: Gate 3 packaged acceptance
→ Hermetic module + test report
First AlGaAs MTP integration on reticle-scale die. Passive cooling sufficient. LoCA windows populated at foundry; nonlinear fill at QLT BEOL.
AssemblyFoundry requirements & intake gates
What the foundry receives vs. what QLT retains. Partial GDS via encrypted transport.
| Item | Requirement / status |
|---|---|
| Primary | LIGENTEC AN350 full reticle |
| Near-term engagement | Listed in immediate foundry packet with GEMINI/TETRIS/NOVA |
| MTP | AlGaAs coupon route R2 fallback if blanket MTP yield low |
| DRC | Reticle fill rules — MRC density audit required |
| Gates | Gate 0 partial GDS + LoCA coupon TST-LoCA |
Campaign intake gates (all chips)
| Gate | Requirement | Status |
|---|---|---|
| Intake checklist | 00-FOUNDRY-INTAKE-CHECKLIST.md completed per chip/foundry | Open |
| NDA / PDK | DKLA executed; active rule deck downloaded and versioned | Open |
| Gate 0 | Partial-GDS export, DRC/LVS, Q-layer strip audit, SHA-256 hash | Open |
| Wafer probe / KGD | Per-die disposition traveler (mandatory NOVA+) | Open / N/A |
| Package ICD | Fiber, electrical, thermal, mechanical interfaces as drawings | Open |
| ATP / OQC | Acceptance matrix, soak, fiber pull, hermetic/leak tests | Open |
| Foundry acceptance | Module order, waiver list, COA format, quote in writing | Open |
Open items FQ-01–FQ-08 centralized in 00-FOUNDRY-INTAKE-CHECKLIST.md §9. PDK assumption freeze (AN350/AN800 layer integers, LoCA limits, CD/overlay) is a hard hold before GDS upload. Partial-GDS boundary must be DRC-debuggable without releasing withheld As₂S₃/TFLN/AlGaAs/control maps.
Five-volume structure
Full specs in Foundry Chip Docs/GALAXY/QLT-GALAXY-PADP-Vol-*
| Volume | Title | Research memos |
|---|---|---|
| Vol I | System Architecture | R01–R04 · blocks, encoding, I/O, power/thermal/package |
| Vol II | Physical Architecture | R05–R09 · layer stack, TFLN, LoCA, floorplan, thermal/electrical |
| Vol III | Device Library | R10–R16 · rings, AWG, mesh, couplers, modulators, OPC, detectors |
| Vol IV | Foundry Requirements | R17–R20 · Ligentec/AIM matrix, custom modules, DRC/IP |
| Vol V | Simulation & Tape-Out | R21–R25 · sim plans, GDS roadmap, honesty audit |
Tape-out readiness & honesty audit
X1 AWG scaling, X2 AlGaAs MTP, X3 encoder fidelity — schematic figures only.
No fabricated simulation results are claimed in Vol V — all campaigns status=planned. No GDS beyond v0.1 heritage layouts. No foundry DRC signoff. Promotion path requires closing gates in GALAXY-PADP-ROLLUP.md.
F-X03
F-X04Cross-links
Foundry Chip Docs · Rev B2
On-disk package: Foundry Chip Docs/GALAXY/ · Bundle: _export/QLT-PADP-RevB2-2026-06-11.zip