Role in QLT Fabrication
The thermal oxidation furnace grows the buried oxide (BOX) layer — a 3–4 µm thick film of thermally grown SiO₂ on bare silicon wafers. This is the very first deposition step in the QLT fabrication flow and establishes the optical foundation for the entire photonic integrated circuit. The BOX layer serves as the lower cladding, confining optical modes within the Si₃N₄ waveguide core and preventing evanescent field leakage into the high-index silicon substrate (n = 3.48 at 1550 nm).
Thermal oxidation produces the highest-quality SiO₂ available in semiconductor fabrication: dense, stoichiometric, pinhole-free, with refractive index of exactly 1.46 at 1550 nm. No other deposition method (PECVD, LPCVD TEOS, sputtering) matches the optical quality of thermally grown oxide. For quantum photonic applications, this quality is non-negotiable — any defects or absorption in the BOX layer would scatter or absorb photons propagating in the evanescent tail of the waveguide mode.
- Optical isolation ● 4 µm BOX provides > 60 dB suppression of substrate leakage for fundamental TE mode at 1550 nm
- Mode confinement ● Refractive index contrast (n_SiN = 2.0, n_BOX = 1.46) enables tight mode confinement in 800 nm × 350 nm waveguides
- Mechanical support ● Dense thermal oxide provides rigid support for Si₃N₄ core and subsequent layers
- Etch stop ● BOX layer serves as etch stop during Poovey switch release etch (HF vapor undercut)
- Stress buffer ● Compressive SiO₂ partially compensates the high tensile stress of LPCVD Si₃N₄
Why Thermal Oxide (Not CVD Oxide)
BOX Layer Requirements
Oxidation Chemistry
THERMAL OXIDATION PROCESS:
DRY OXIDATION (O₂ ambient):
├── Reaction: Si + O₂ → SiO₂
├── Temperature: 900–1100°C
├── Rate: very slow (~0.02 µm/hr at 1100°C for thick oxides)
├── Quality: highest density, lowest defect count
└── Used for: thin gate oxides (5–50 nm)
WET OXIDATION (H₂O ambient — our method for BOX):
├── Reaction: Si + 2H₂O → SiO₂ + 2H₂
├── Temperature: 1000–1100°C
├── Rate: 5–10× faster than dry (Deal-Grove model)
│ └── ~0.15 µm/hr at 1100°C for 4 µm target
├── Quality: slightly lower density than dry; still excellent
├── Steam generation: pyrogenic (H₂ + O₂ torch) or bubbler
└── Time for 4 µm: ~24–30 hours at 1050°C
DEAL-GROVE MODEL:
├── x² + A·x = B·(t + τ)
├── x = oxide thickness, t = time
├── B = parabolic rate constant (diffusion-limited)
├── B/A = linear rate constant (reaction-limited)
├── For thick oxides (> 1 µm): x ≈ √(B·t) [parabolic regime]
└── Temperature dependence: Arrhenius (Ea ~1.2 eV for wet O₂)
SILICON CONSUMPTION:
├── 0.44 × oxide thickness = Si consumed
├── For 4 µm SiO₂: ~1.76 µm of Si is consumed
├── Starting wafer: 500–675 µm thick → negligible impact
└── Oxide grows INTO the silicon (56% above, 44% below original surface)
Process Integration
QLT PROCESS FLOW ● Thermal Oxidation Furnace (Step B1):
PRE-REQUISITES:
├── Bare silicon wafer: 150 mm or 200 mm, (100) orientation, p-type
├── Resistivity: 1–10 Ω·cm (not critical for photonics)
├── Wafer cleaned: full RCA clean sequence
│ ├── SC-1: NH₄OH:H₂O₂:H₂O (5:1:1) @ 75°C, 10 min
│ ├── HF dip: 1% HF, 30 s (strips native oxide)
│ ├── SC-2: HCl:H₂O₂:H₂O (5:1:1) @ 75°C, 10 min
│ └── Final DI water rinse + spin dry
└── Surface must be hydrophobic after HF dip (confirms clean Si)
STEP 1: Furnace Preparation
├── Idle at 800°C under N₂ flow
├── Pre-oxidation clean: TCA (trichloroethane) or HCl/O₂ clean
│ └── Removes mobile ion contamination (Na⁺, K⁺) from tube
├── Verify thermocouple calibration
└── Confirm gas flows: O₂, H₂, N₂
STEP 2: Load Wafer Boat
├── Load 25–100 wafers in quartz boat
├── Include monitor wafers (bare Si) at ends and center
├── Slow push into furnace (1 cm/min)
├── Temperature at loading: 800°C (prevents thermal shock)
└── N₂ ambient during loading (prevents unwanted thin oxide)
STEP 3: Ramp to Oxidation Temperature
├── Ramp: 800°C → 1050°C at 5°C/min
├── Atmosphere: dry N₂ (no oxidation during ramp)
├── Ramp time: ~50 minutes
└── Stabilize at 1050°C for 10 min
STEP 4: Wet Oxidation
├── Switch atmosphere: N₂ → pyrogenic steam (H₂ + O₂ torch)
├── H₂:O₂ ratio: ~1.8:1 (excess H₂ for complete combustion)
├── Temperature: 1050°C
├── Duration: 24–30 hours (for 4 µm target)
├── Monitor oxide color on monitor wafers (4 µm ≈ 3rd-order green)
└── Maintain steady-state gas flows throughout
STEP 5: Anneal & Densification
├── Switch to dry N₂ atmosphere
├── Hold at 1050°C for 30 min (densification)
├── Optional: brief dry O₂ step (improves Si/SiO₂ interface quality)
└── Purpose: densify oxide, reduce interface trap density
STEP 6: Cool-Down & Unload
├── Ramp down: 1050°C → 800°C at 3°C/min (slow to prevent slip)
├── Slow pull from furnace at 800°C
├── Transfer to cooling station
└── Total process time: ~30–36 hours (including ramp/anneal)
STEP 7: Qualification
├── Ellipsometry: thickness = 4.0 ± 0.2 µm, n = 1.46
├── Uniformity map: < 2% across wafer
├── AFM: surface roughness < 0.2 nm RMS
├── Visual: uniform color across all wafers
└── Breakdown test (sample): > 10 MV/cm
SUBSEQUENT STEPS:
└── Wafer proceeds to LPCVD Si₃N₄ deposition (Step B2)
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Safety & Handling
Hazard Summary
Emergency Procedures
H₂ LEAK RESPONSE:
1. EVACUATE the area immediately — H₂ is odorless and highly flammable
2. Do NOT operate electrical switches (potential ignition source)
3. Pull emergency gas shut-off (EMO) if safely accessible
4. Call facility emergency response / fire department
5. H₂ sensor should trigger auto-shutoff at 25% LEL (1% H₂ in air)
6. H₂ rises rapidly — ventilate at ceiling level
7. Do NOT re-enter until gas monitors confirm safe atmosphere
8. After clearance: leak-check all H₂ lines and torch assembly
9. Document incident per EH&S reporting requirements
FURNACE OVER-TEMPERATURE:
1. Auto-shutdown should trigger via over-temp thermocouple
2. Do NOT open furnace door (thermal shock risk to quartz tube)
3. Shut off power at breaker if controller fails
4. Allow controlled cool-down under N₂ flow
5. Inspect heating elements and thermocouples before restart