Scanning Electron Microscope

Role in QLT Fabrication

The scanning electron microscope is the primary metrology instrument for verifying every patterned feature on the QLT photonic chip. Si₃N₄ waveguide performance at 1550 nm is dominated by sidewall roughness — even 1 nm RMS roughness increase can raise propagation loss from 0.5 dB/m to > 2 dB/m through Rayleigh scattering at the core-cladding interface. The SEM provides the sub-nanometer resolution needed to directly image these surfaces and feed corrective data back into the etch process.

Beyond waveguide sidewalls, the SEM is indispensable for characterizing every critical dimension on the chip:

• Waveguide width verification ● 900 nm bus waveguides require ±10 nm control for single-mode operation at 1550 nm
• Etch depth profiling ● full-etch (350 nm) and shallow-etch (150 nm) depths measured in cross-section with < 2 nm accuracy
• Photonic crystal hole profiles ● hole diameter, pitch, and sidewall verticality of grating coupler features
• Poovey switch trench inspection ● 34 µm × 20 µm oxide trench geometry, 250 nm air-gap uniformity between released arms
• Metallization quality ● TiN heater line-edge roughness, Au contact pad adhesion, wire-bond pull-test correlation
• As₂S₃ overlay interface ● cross-sectional imaging of the hybrid SiN/As₂S₃ boundary to verify interface roughness < 1 nm RMS
• Particle and defect detection ● locating contaminants, etch residues, and delamination on patterned surfaces

Why Field-Emission SEM (Not Optical Microscopy)

Critical Measurement Requirements

Technical Specifications

Thermo Fisher Helios G4 UX DualBeam

Hitachi SU8230 Cold Field-Emission SEM

Detector Selection for QLT Applications

Process Integration

QLT PROCESS FLOW ● SEM Metrology (Step 07):

INSPECTION POINTS IN FABRICATION SEQUENCE:
├── Post-lithography (resist inspection)
│   ├── Verify resist profile and dimensions before etch
│   ├── Low-kV imaging (0.5–2 kV) to avoid resist damage
│   └── GO/NO-GO gate for etch step
│
├── Post-RIE etch (waveguide definition)
│   ├── Sidewall roughness measurement (tilted 80–85°)
│   ├── Critical dimension (CD) verification at 5 sites per chip
│   ├── Etch depth via cross-section (cleave or FIB)
│   └── Etch recipe feedback: adjust CHF₃/O₂ ratio if needed
│
├── Post-CMP planarization
│   ├── Surface roughness verification
│   ├── Dishing/erosion at waveguide edges
│   └── Particle count on polished surface
│
├── Post-Poovey trench release
│   ├── Trench geometry: 34 µm × 20 µm, depth 3.3 µm
│   ├── Air gap measurement between released and fixed arms
│   ├── Verify no stiction (released arm free-standing)
│   └── Anchor pad integrity check
│
├── Post-metallization (TiN heaters, Au pads)
│   ├── Line-edge roughness of TiN heater traces
│   ├── Step coverage at topography transitions
│   ├── Contact pad morphology
│   └── Wire-bond pad surface quality
│
├── Post-As₂S₃ deposition (GAP03 module)
│   ├── Cross-section: overlay thickness (500 ± 20 nm)
│   ├── Interface roughness at SiN/As₂S₃ boundary
│   ├── EDS linescan for stoichiometry (As:S ratio ≈ 2:3)
│   └── Edge definition of patterned overlay
│
└── Final inspection (pre-dicing)
    ├── Full die overview at low magnification
    ├── Representative high-mag images for traveler documentation
    └── Defect map for yield analysis

SEM Sample Preparation

SAMPLE PREPARATION PROTOCOLS:

TOP-DOWN IMAGING (non-destructive):
├── Mount chip on SEM stub with carbon tape
├── Optional: 2–5 nm Pt/Pd sputter coat for insulators
│   └── Skip for conductive layers (TiN, Au)
├── Load into SEM chamber, pump to < 10⁻⁵ mbar
└── Imaging time: 15–30 min per chip (5–10 sites)

CROSS-SECTION (cleave method — destructive):
├── Score backside of wafer with diamond scribe
├── Cleave through region of interest
├── Mount on 90° stub, tilt to 0° (viewing cleaved face)
├── Optional: brief plasma clean (Ar, 30 s) to remove debris
└── Fast turnaround: ~1 hour total

CROSS-SECTION (FIB method — site-specific, destructive):
├── Deposit protective Pt strap (2 µm thick) over ROI
├── FIB trench: 30 kV, 20 nA rough cut → 1 nA fine polish
├── Thin to ~100 nm for STEM, or image in-situ for SEM
├── Total FIB prep time: 2–4 hours
└── Best for: waveguide stack cross-section at specific location

Vendor Options & Pricing

New System Pricing

Refurbished Market

Vendor Directory

Facility Requirements

Space and Utilities

Infrastructure Costs

Safety & Handling

Hazard Summary

Operating Procedures

SEM OPERATIONAL SAFETY:

PRE-OPERATION:
├── Verify all interlocks engaged (chamber door, HV cover)
├── Check vacuum status — do NOT open chamber above 10⁻³ mbar
├── Confirm chiller is running and at temperature (18–22°C)
├── Log session in SEM logbook (user, date, sample ID)
└── Wear nitrile gloves when handling samples (prevent contamination)

DURING OPERATION:
├── Do NOT leave FIB milling unattended for extended periods
├── Monitor beam current — excessive current damages thin samples
├── For EDS: confirm X-ray shielding indicators are active above 5 kV
├── Save all images with metadata (kV, WD, mag, detector)
└── For As₂S₃ samples: minimize beam exposure (beam-sensitive material)

POST-OPERATION:
├── Retract stage to safe position
├── Blank electron beam and FIB column
├── Vent chamber with dry N₂ (slow vent, 2–3 min)
├── Remove sample; return to wafer carrier
├── Log end time and any issues in logbook
└── If GIS was used: record precursor level for tracking