Role in QLT Fabrication
The Precision Micro-Assembly Station performs the most mechanically demanding step in QLT's post-foundry fabrication flow: the deterministic pick-and-place of prefabricated all-optical Poovey-switch nano-stacks into lithographically defined waveguide trenches on the Si₃N₄ photonic chip. Each nano-stack — a layered structure of PZT piezoelectric film, Ti/Au electrodes, and released SiN rib segments — must land within ±200 nm of its target position to ensure sub-wavelength evanescent coupling between the fixed bus waveguide and the actuated switching arm.
This station bridges the gap between foundry-delivered wafer processing and functional device integration. Unlike monolithic deposition steps (PECVD, sputtering, evaporation), micro-assembly is an inherently serial, component-level operation requiring real-time visual feedback, sub-micron manipulator control, and controlled bonding conditions. The station combines:
- High-magnification optical inspection ● ≥200× microscope with coaxial illumination resolves the 250 nm air-gap geometry and vernier alignment marks on both the chiplet and the host trench
- 6-axis micro-manipulator ● X, Y, Z translation plus θ (yaw), φ (pitch), and ψ (roll) rotation for full pose correction of the nano-stack before placement
- Vacuum pick-up tooling ● Custom collet tips (10–50 μm bore diameter) securely grip the nano-stack without contacting the active PZT surface or waveguide facets
- Thermocompression bonding head ● Controlled force (0.1–5 N) and temperature (up to 300°C) for AuSn or epoxy-based die-attach at the trench floor
- Pattern-recognition alignment ● Machine-vision software locks onto foundry-defined vernier crosses for automated fine alignment, reducing operator dependence
- Vibration-isolated granite base ● Passive pneumatic isolation (0.5–2 Hz resonance) eliminates building vibration that would exceed the ±200 nm placement tolerance
Why Micro-Assembly (Not Monolithic Integration)
The Poovey all-optical switch requires a released SiN rib with a PZT bimorph actuator — a structure that cannot be fabricated monolithically on the foundry wafer without destroying prior layers. The PZT film (60 nm Pb(Zr₀.₅₂Ti₀.₄₈)O₃) requires 600–700°C crystallization anneal, which would damage TiN heaters, Au contact pads, and any temperature-sensitive waveguide cladding already on the chip. Separately fabricating the nano-stacks on a dedicated carrier wafer and then transferring them into the host chip trenches is the only viable integration strategy.
Nano-Stack Architecture
Each Poovey-switch nano-stack is a pre-fabricated chiplet measuring approximately 34 μm × 20 μm × 4 μm, assembled on a sacrificial carrier and released before pick-up. The stack consists of:
Technical Specifications
Micro-Assembly Station Core Specifications
Optical Subsystem Specifications
Placement Tolerance Budget
PLACEMENT ERROR BUDGET — Poovey Switch Nano-Stack:
Target air gap (OFF state): 250 nm ± 25 nm
Coupling length tolerance: ±0.5 μm (over 29 μm interaction length)
Anchor pad registration: ±0.3 μm (to SiO₂ trench sidewall)
Error Source Allocation (3σ) Method
─────────────────────────────────────────────────────────────────
Machine vision registration ±80 nm Pattern recognition on verniers
Manipulator positioning ±60 nm Closed-loop piezo + encoder
Thermal drift (30 min session) ±40 nm Granite base + temp stabilization
Bond force induced shift ±30 nm Force-controlled touchdown
Adhesive/solder creep ±20 nm AuSn eutectic (rigid)
Vibration (during placement) ±15 nm Pneumatic isolation table
─────────────────────────────────────────────────────────────────
RSS Total: ±118 nm Within ±200 nm budget ✓
CRITICAL ALIGNMENT FEATURES:
├── Vernier crosses: 4× per trench site (foundry-defined, ±0.5 μm to WG_FULL layer)
├── Nano-stack fiducials: Au L-marks on carrier die corners
├── Gap verification: Post-placement SEM cross-section (destructive, on test sites)
└── Optical verification: Top-down microscope measures anchor-to-edge distance
Process Integration
QLT PROCESS FLOW ● Micro-Assembly Station (Step 04):
PRE-REQUISITES:
├── Host chip: foundry wafer with trenches etched (34 μm × 20 μm × 3.3 μm)
│ └── Trench floor cleaned (O₂ plasma descum, 100 W, 30 s)
├── Nano-stacks: PZT/electrode/SiN chiplets on carrier gel-film or blue tape
│ └── Released from sacrificial layer; inspected under microscope
├── Die-attach material prepared:
│ ├── Option A: AuSn preform (80/20, 3 μm thick, laser-cut to 30 μm × 16 μm)
│ └── Option B: UV-cure epoxy (Dymax OP-67-LS, needle-dispensed, <0.5 nL)
└── Station warmed up: thermal drift settled (>30 min power-on)
STEP 1: Host Chip Loading
├── Place host chip/die on vacuum chuck (porous ceramic, 150 mm)
├── Enable zone vacuum under die area (−600 mbar)
├── Focus microscope on trench site #1
├── Run automatic fiducial detection (4 vernier crosses per trench)
├── Record substrate coordinate system origin
└── Verify trench cleanliness at 200×: no particles > 0.5 μm
STEP 2: Nano-Stack Pick-Up
├── Position carrier film on source stage (adjacent to host chuck)
├── Focus on target nano-stack at 50× magnification
├── Lower vacuum collet (10 μm bore) to nano-stack surface
│ ├── Approach rate: 2 μm/s (final 20 μm)
│ └── Contact detection: force sensor threshold at 0.5 mN
├── Enable collet vacuum (−400 mbar) → grip nano-stack
├── Retract collet Z: 200 μm lift-off
└── Verify pick-up: inspect under collet camera (nano-stack attached, no rotation)
STEP 3: Coarse Alignment
├── Traverse manipulator X-Y to host chip trench site
├── Lower collet to 50 μm above trench surface
├── Switch to split-optics mode:
│ ├── Upper image: nano-stack bottom surface (fiducial L-marks)
│ └── Lower image: trench alignment verniers (foundry-defined)
├── Overlay images on monitor → coarse align to ±5 μm
└── Switch to 200× magnification for fine alignment
STEP 4: Fine Alignment (Pattern Recognition)
├── Machine vision locks onto vernier cross-pairs
├── Software computes X, Y, θ correction vectors
├── Piezo actuators apply correction in closed loop:
│ ├── X, Y correction: ±0.2 μm steps until <100 nm residual
│ └── θ correction: ±0.005° steps until <0.01° residual
├── Operator confirms alignment on live overlay display
└── Record pre-bond position: X = ___, Y = ___, θ = ___
STEP 5: Die Attach (Thermocompression or Adhesive)
├── OPTION A — AuSn Eutectic Bond:
│ ├── Pre-placed AuSn preform on trench floor (from Step 1)
│ ├── Ramp substrate heater: RT → 280°C (below AuSn liquidus at 280°C)
│ ├── Lower collet at 0.5 μm/s → contact trench floor (force: 0.5–2 N)
│ ├── Ramp to 310°C (5°C/s) → AuSn reflows → metallic bond forms
│ ├── Hold 310°C for 10 s under 1 N force
│ ├── Cool to 200°C → release collet vacuum → retract
│ └── Cool to RT (natural, ~3 min)
├── OPTION B — UV-Cure Epoxy Bond:
│ ├── Dispense 0.3–0.5 nL epoxy at trench anchor pads (pre-placement)
│ ├── Lower collet at 0.5 μm/s → seat nano-stack into trench
│ ├── Apply 0.2 N contact force for 5 s (spreads adhesive)
│ ├── UV flood expose: 365 nm, 3 W/cm², 30 s → epoxy cures
│ ├── Release collet vacuum → retract
│ └── Optional: thermal post-cure 120°C, 30 min (batch after all placements)
└── Record bond parameters: force, temp, time
STEP 6: Post-Placement Verification
├── Microscope inspection at 200×:
│ ├── Vernier readout: alignment ≤ ±200 nm (X, Y)
│ ├── Rotation check: θ ≤ ±0.01°
│ ├── Anchor pad contact: continuous bond line visible
│ └── No particulate contamination on waveguide rib
├── Electrical continuity: probe top/bottom electrode (R < 50 kΩ confirms PZT intact)
├── Repeat Steps 2–6 for remaining trench sites on this die
│ └── Typical: 4–16 Poovey switch sites per 5 mm × 5 mm die
└── PASS: All placements within ±200 nm; all PZT stacks electrically intact
STEP 7: Wire Bonding (Separate Station)
├── Transfer assembled die to wire bonder
├── Au wedge bond: 25 μm wire, top electrode pad → chip bond pad
├── Ball-stitch sequence: 4 bonds per switch (2 electrodes × 2 redundant)
└── Pull-test: >3 gf per bond
Vendor Options & Pricing
New System Pricing
Refurbished & Used Market
Custom Build Option (Component-Level)
For maximum flexibility and lowest upfront cost, QLT can build a custom micro-assembly station from commercial sub-components. This approach trades throughput and automation for configurability and access to the exact specifications needed for Poovey-switch placement.
Vendor Directory
Facility Requirements
Cleanroom & Environment
⚠️ VIBRATION ISOLATION IS THE #1 FACILITY REQUIREMENT ⚠️
The ±200 nm placement tolerance is comparable to typical building
vibration amplitudes (100–500 nm at 10–30 Hz). Without proper
isolation, placement accuracy degrades to ±1–5 μm — 5–25× worse
than the specification.
VIBRATION ISOLATION HIERARCHY:
├── Level 1: Pneumatic isolation table legs (TMC, Newport, Thorlabs)
│ └── Reduces floor vibration by 20–40 dB above 2 Hz
│ └── Cost: $8,000–$20,000 (included in granite base quote)
├── Level 2: Ground floor / concrete slab on grade
│ └── Eliminates inter-floor structural resonances (8–15 Hz)
│ └── Required if upper-floor placement shows excess vibration
├── Level 3: Dedicated inertia block (1+ ton concrete pier)
│ └── For extreme environments (near HVAC, compressors, traffic)
│ └── Cost: $5,000–$15,000 (civil works)
└── Level 4: Active vibration cancellation (Herzan, TMC STACIS)
└── Reduces vibration to <1 nm above 1 Hz
└── Cost: $15,000–$40,000 (overkill for our application)
Space and Utilities
Infrastructure Cost Summary
Safety & Handling
Hazard Summary
ESD Protection Protocol
⚠️ PZT NANO-STACKS ARE ESD-SENSITIVE ⚠️
PZT thin-film electrodes (55 nm Au top / 25 nm Pt bottom) can be
damaged by discharges as low as 50V. The piezoelectric film itself
can be de-poled by static fields exceeding the coercive field
(~50 kV/cm → only 30V across 60 nm film).
MANDATORY ESD CONTROLS:
├── Operator grounding: wrist strap + heel straps (verified daily)
├── Station grounding: all metal surfaces bonded to facility ground
├── Ionizing air bar: positioned over work area (Simco-Ion or equiv.)
│ └── Reduces surface charge to <25V within 2 s
├── ESD-safe storage: nano-stacks in conductive gel-paks or waffle trays
├── Collet tip material: conductive ceramic or grounded metal
├── Humidity ≥ 35% RH: prevents charge accumulation
└── Handling: NEVER touch nano-stacks with ungrounded tools or tweezers
ESD VERIFICATION:
├── Daily wrist strap check (resistance: 0.8–10 MΩ to ground)
├── Weekly surface voltage audit (<100V on all workstation surfaces)
└── Incoming nano-stack lot sample: measure PZT capacitance (250±50 pF)
to confirm no ESD damage during shipping
Handling Best Practices
- Nano-stack storage ● Keep on carrier film in conductive waffle tray; store in N₂ desiccator cabinet (<5% RH) to prevent Au pad oxidation
- Collet maintenance ● Inspect vacuum tip under 50× microscope before each session; replace if chipped or contaminated; ultrasonic clean in IPA weekly
- Force calibration ● Verify force sensor zero and linearity quarterly using NIST-traceable calibration weights (0.1–10 N range)
- Thermal calibration ● Verify bond head and substrate heater temperatures with Type-K thermocouple quarterly; ±2°C from setpoint is acceptable
- Microscope alignment ● Verify parfocality between 50× and 200× monthly; recalibrate if overlay offset exceeds 2 μm
- Vibration check ● If placement accuracy degrades, run accelerometer survey (Wilcoxon 786A or equiv.) at 1–100 Hz; compare to VC-D criterion
- Emergency bond abort ● If misalignment detected after bond force is applied but before reflow temperature: retract immediately (collet Z-up); nano-stack can be re-picked if adhesive has not cured