Role in QLT Fabrication
As QLT's quantum photonic processor scales beyond the initial 8-mode single-die architecture, advanced packaging becomes essential for integrating multiple heterogeneous chiplets — photonic mesh dies, SPAD detector arrays, TDC readout ASICs, and control electronics — into a single multi-chip module (MCM). Traditional wire bonding suffices for v1 prototypes, but Phase 3 production demands flip-chip bonding with sub-micron alignment accuracy, through-silicon vias for vertical electrical interconnect, and silicon or glass interposers for 2.5D co-integration.
The advanced packaging station replaces long wire-bond paths (which add parasitic inductance and limit bandwidth) with short solder-bump interconnects that can handle the >1 GHz signaling rates required for real-time herald-to-switch feedback loops. This is a Phase 3 investment — the v1/v2 prototypes use conventional wire bonding and separate PCB assemblies.
- Flip-chip bonding ● sub-5 μm placement accuracy for photonic die-to-interposer alignment
- TSV integration ● vertical electrical paths through silicon interposer eliminate wire bonds
- 2.5D interposer ● co-locates photonic die, SPAD array, and TDC ASIC within 1 mm
- Thermal management ● copper pillar bumps provide direct thermal path to heat spreader
- Signal integrity ● bump pitch < 100 μm enables >10 GHz electrical bandwidth
- Scalability ● enables 16-mode and 32-mode multi-die processor assemblies
Why Advanced Packaging for Quantum Photonics?
Technical Specifications
Flip-Chip Bonder — Primary Tool
2.5D Interposer Architecture for QLT
QLT MULTI-CHIP MODULE (Phase 3 Architecture):
┌─────────────────────────────────────────────────────┐
│ Kovar Package Lid │
├─────────────────────────────────────────────────────┤
│ │
│ ┌──────────┐ ┌──────────┐ ┌──────────────┐ │
│ │ PHOTONIC │ │ SPAD │ │ TDC ASIC │ │
│ │ MESH DIE │ │ ARRAY │ │ (PACIFIC-2) │ │
│ │ 5×5 mm │ │ 2×2 mm │ │ 3×3 mm │ │
│ └────┬─────┘ └────┬─────┘ └──────┬───────┘ │
│ │bump │bump │bump │
│ ═════╪══════════════╪═══════════════╪═══════ │
│ │ SILICON INTERPOSER (15×15 mm) │ │
│ │ TSVs + RDL (redistribution layer) │ │
│ │ Fine-pitch wiring: 2 μm L/S │ │
│ ═════════════════════════════════════════════ │
│ │C4 bumps │
│ ┌────┴────────────────────────────────────┐ │
│ │ ORGANIC SUBSTRATE (BGA) │ │
│ │ 0.8 mm core, 6-layer buildup │ │
│ └──────────────────────────────────────────┘ │
│ │BGA balls │
├─────────────────────────────────────────────────────┤
│ AlN Sub-mount / Heat Spreader │
└─────────────────────────────────────────────────────┘
KEY ADVANTAGES:
├── Photonic ↔ SPAD optical path: < 2 mm (on-interposer waveguide)
├── SPAD → TDC electrical path: < 500 μm (interposer RDL)
├── Herald latency reduction: 11.2 ns → < 5 ns (shorter paths)
├── Thermal: all dies share common heat sink via Cu TSVs
└── I/O: 500+ connections between dies (impossible with wire bond)
Through-Silicon Via (TSV) Specifications
Process Integration
QLT ADVANCED PACKAGING FLOW (Phase 3):
PRE-REQUISITES:
├── Photonic die: tested, diced, known-good-die (KGD)
├── SPAD array die: KGD, bumped with In or AuSn
├── TDC ASIC: KGD, Cu pillar bumped (40 μm pitch)
├── Silicon interposer: TSV-processed, RDL patterned, bumped
└── All dies have fiducial alignment marks
STEP 1: Interposer Preparation
├── Inspect interposer under automated optical inspection (AOI)
├── Verify TSV continuity (4-wire probe, sample basis)
├── Apply flux or no-clean paste to micro-bump pads
└── Mount interposer on bonding chuck (vacuum hold)
STEP 2: Photonic Die Placement (Critical Alignment)
├── Pick photonic die from waffle tray
├── Dual-camera alignment: top fiducials + bottom fiducials
├── Place at ±1.5 μm accuracy onto interposer
├── Thermocompression bond: 300°C, 20 N, 10 s
└── Optical alignment CRITICAL: waveguide ↔ interposer coupler
STEP 3: SPAD Array Placement
├── Pick SPAD die from gel-pack
├── Align to interposer optical I/O pads
├── Bond: AuSn reflow at 310°C or In cold-weld at 150°C
└── In bumps preferred (lower temp protects photonic die)
STEP 4: TDC ASIC Placement
├── Pick TDC ASIC (PACIFIC-2) from waffle tray
├── Standard electrical alignment (less critical than photonic)
├── Thermocompression bond: 280°C, 15 N, 8 s
└── Cu pillar + SnAg cap reflow
STEP 5: Underfill Dispense
├── Capillary underfill (Namics U8443-14) between each die pair
├── Cure: 150°C × 30 min
├── Protects bumps from thermal cycling stress
└── CTE-matched filler for reliability
STEP 6: Interposer-to-Substrate Attach
├── C4 solder balls on interposer backside
├── Mass reflow onto organic BGA substrate
├── Peak reflow: 260°C (Pb-free SAC305)
└── X-ray inspection for void content < 25%
STEP 7: Package-Level Assembly
├── Mount MCM substrate into Kovar package
├── Attach fiber arrays to photonic die edge couplers
├── Hermetic seal (seam weld per hermetic-packaging process)
└── Final electrical + optical test
Vendor Options & Pricing
Flip-Chip Bonder Systems
Supporting Equipment
Total System Budget
PHASE 3 ADVANCED PACKAGING LINE:
Core flip-chip bonder: $600,000–$1,200,000
Underfill dispenser: $80,000–$150,000
Reflow oven: $100,000–$200,000
X-ray inspection: $200,000–$400,000
Plasma cleaner: $30,000–$60,000
Interposer procurement: $200–$500/unit (outsource TSV)
Installation & qualification: $50,000–$100,000
═══════════════════════════════════════════
ESTIMATED TOTAL: $2,000,000–$3,000,000
═══════════════════════════════════════════
ALTERNATIVE: Outsource to OSAT
├── Amkor Technology (Tempe, AZ)
├── ASE Group (Taiwan)
├── JCET (China)
├── Cost: $500–$2,000/MCM (depending on complexity)
├── NRE: $50,000–$200,000 (mask set + qualification)
└── Recommended for < 1,000 units/year